stdp_synapse_facetshw_hom – Synapse type for spike-timing dependent plasticity using homogeneous parameters =========================================================================================================== Description +++++++++++ ``stdp_facetshw_synapse`` is a connector to create synapses with spike-timing dependent plasticity (as defined in [1]_). This connector is a modified version of ``stdp_synapse``. It includes constraints of the hardware developed in the FACETS (BrainScaleS) project [2]_, [3]_, as for example, 4-bit weight resolution, sequential updates of groups of synapses and reduced symmetric nearest-neighbor spike pairing scheme. For details see [3]_. The modified spike pairing scheme requires the calculation of ``tau_minus_`` within this synapse and not at the neuron site via ``Kplus_`` like in ``stdp_synapse_hom``. .. warning:: This synaptic plasticity rule does not take :ref:`precise spike timing ` into account. When calculating the weight update, the precise spike time part of the timestamp is ignored. The synapse IDs are assigned to each synapse in an ascending order (0,1,2, ...) according their first presynaptic activity and is used to group synapses that are updated at once. It is possible to avoid activity dependent synapse ID assignments by manually setting the no_synapses and the synapse_id(s) before running the simulation. The weights will be discretized after the first presynaptic activity at a synapse. Parameters ++++++++++ ======================= =========== =========================================== **Common properties** ------------------------------------------------------------------------------- tau_plus ms Time constant of STDP window, causal branch tau_minus_stdp ms Time constant of STDP window, anti-causal branch Wmax real Maximum allowed weight no_synapses integer Total number of synapses synapses_per_driver integer Number of synapses updated at once driver_readout_time real Time for processing of one synapse row (synapse line driver) readout_cycle_duration real Duration between two subsequent updates of same synapse (synapse line driver) lookuptable_0 list of Three look-up tables (LUT) integers lookuptable_1 list of integers lookuptable_2 list of integers configbit_0 list of Configuration bits for evaluation integers function. For details see code in function ``eval_function_`` and [4]_ (configbit[0]=e_cc, ..[1]_=e_ca, ..[2]_=e_ac, ..[3]=e_aa). Depending on these two sets of configuration bits weights are updated according LUTs (out of three: (1,0), (0,1), (1,1)). For (0,0) continue without reset. configbit_1 list of integers reset_pattern list of Configuration bits for reset behavior. integers Two bits for each LUT (reset causal and acausal). In hardware only (all false; never reset) or (all true; always reset) is allowed. ======================= =========== =========================================== Common properties can only be set on the synapse model using :py:func:`.SetDefaults`. ============ ======= ===================================================== **Individual properties** --------------------------------------------------------------------------- a_causal real Causal and anti-causal spike pair accumulations a_acausal real a_thresh_th real Two thresholds used in evaluation function No common property, because variation of analog synapse circuitry can be applied here a_thresh_tl real synapse_id integer Synapse ID, used to assign synapses to groups (synapse drivers) ============ ======= ===================================================== Transmits +++++++++ SpikeEvent References ++++++++++ .. [1] Morrison A, Diesmann M, Gerstner W (2008). Phenomenological models of synaptic plasticity based on spike-timing. Biological Cybernetics, 98:459-478. DOI: https://doi.org/10.1007/s00422-008-0233-1 .. [2] Schemmel J, Gruebl A, Meier K, Mueller E (2006). Implementing synaptic plasticity in a VLSI spiking neural network model. In Proceedings of the 2006 International Joint Conference on Neural Networks, pp.1--6, IEEE Press. DOI: https://doi.org/10.1109/IJCNN.2006.246651 .. [3] Pfeil T, Potjans TC, Schrader S, Potjans W, Schemmel J, Diesmann M, Meier K (2012). Is a 4-bit synaptic weight resolution enough? - constraints on enabling spike-timing dependent plasticity in neuromorphic hardware. Frontiers in Neuroscience 6(90). DOI: https://doi.org/10.3389/fnins.2012.00090 .. [4] Friedmann, S. in preparation See also ++++++++ :doc:`Synapse `, :doc:`Spike-Timing-Dependent Plasticity `